TM 9-4935-481-14-1
C2
(g) This circuit reference fig. 4-49 (schematic, sheet 2) consists of retriggerable monostable multivibrators Z18,
Z22, Z23 and Z25 and clocked flip flop Z20 and other logic elements. The circuit is tested by applying a step input LOW
NOTE
(<0.4 Vdc) and/or a step input HIGH (>2.5 Vdc) to the appropriate input pins on the circuit card and monitoring the output
pins for the proper waveform or logic level. The nominal output pulsewidth of Z18, Z22, Z23 and Z25 is 5.1 psec, 1.6 -sec,
The waveforms shown in fig. 4-50 (schematic) are system waveforms which are
5.1 psec and 34.2 psec, respectively. The nominal time delay of logic elements Z24, Z21 (pin 6) and Z21 (pin 8) is 9.5 psec,
applicable to the circuit performance when the assembly is installed in DMS-D, but
1.4 -sec and 658 psec, respectively. The circuit is reset by applying a LOW to P1-107.
which do not necessarily apply to the circuit performance while tested in DMS-G.
NOTE
(12) Vertical pulse simulator C - A12 (fig. 4-51)
The waveforms shown in fig. 4-49 (schematic) are system waveforms which are
The A12 circuit card is performance tested using DMS-D, DMS-G and test adapter A12, connector J3.
applicable to the circuit performance when the assembly is installed in DMS-D, but
(a) This circuit card generates the first pulse timing, and pulsewidth required for testing the tracker test set
which do not necessarily apply to the circuit performance while tested in DMS-G.
vertical guidance wire test circuits. The circuit card also contains some vertical wire clock control logic circuits and logic for
steering the trigger output circuits. A description of the digital logic circuits will be found in Chapter 3, paragraph 3-3 (b
through h) of this manual.
(11) Vertical pulse simulator B - A11 (fig. 4-50)
(b) The circuit card is tested by applying a step input LOW (<0.4 Vdc) and/ or a step input HIGH (>2.5 Vdc) to
The All circuit card is performance tested using DMS-D, DMS-G and test adapter A12, connector J2.
the appropriate input pins on the circuit card and measuring for a HIGH or a LOW (whichever is required) on the
corresponding output pins.
(a) This circuit card is used to generate the pulse repetition rate timing and the pulse width timing required to
performance test the tracker test set. A description of the digital logic circuits will be found in Chapter 3, paragraph 3-3 (b
(c) Z10 and Z11 are retriggerable monostable multivibrators which have a pulsewidth of 21.86 msec and 66
through h) of this manual.
ec, respectively. Z9 (pin 8) has a time delay of 658 psec (nominal) and Z9 (pin 6) has a time delay of 95 -sec (nominal).
s
(b) The circuit card is tested by applying a step input LOW (<0.4 Vdc) and/ or a step input HIGH (>2.5 Vdc) to the
appropriate input pins on the circuit card and measuring for a HIGH or a LOW (whichever is required) on the corresponding
out- put pins.
NOTE
(c) Z10 is a retriggerable monostable multivabrator that has an output pulsewidth of 1.609 psec (nominal).
The waveforms shown in fig. 4-51 (schematic) are system waveforms which are
applicable to the circuit performance when the assembly is installed in DMS-D, but
which do not necessarily apply to the circuit performance while tested in DMS-G.
(13) Vertical pulse simulator D - A13 (fig. 4-52)
The A13 circuit card is performance tested using DMS-D, DMS-G and test adapter All, connector J4.
(a) This circuit card generates the vertical guidance wire pulse amplitude and the horizontal guidance wire clamp
voltage required for testing the tracker test set.
3-30.8