C4
TM9-4935-481-14-1
potentiometer R15.
desirable to have control of the clock and counters so that measurements can be made at any fixed point in time. This is
(3) Internal test. Self-test of the DMS-D is accomplished with the aid of internal test switch S33. A total of thirty
accomplished by means of counter inhibit (sec) thumbwheel switch S31, and run/hold/off switch S32.
functions are performed by the various positions of the switch, as described in table 3-6.
(a) The DMS-D counter inhibit thumbwheel switch decade counters are first decoded so that their normal 1, 2, 4
3-3.
DMS Electrical and Electronic Circuit Analysis .
and 8 binary outputs are transformed into 0 through 9 decimal outputs. These signals are then routed to the individual decks
of S31 so that when the switch outputs are logically summed, a signal will be generated that will correspond in time to the dial
settings. The inhibit time may be set at any point between 0.01 seconds and 29.99 seconds in 0.01 second increments, thus
a. General. Operation of the PC card assemblies in the DMS is explained in subsequent paragraphs. This paragraph
resulting in complete control over the timing logic.
explains basic circuits used throughout the various circuit cards. Comprehension of these circuits, as used in the DMS, will
enhance troubleshooting and subsequent repair of the PC card assemblies. Later paragraphs describe the testing and
(b) When advancing the counter from one time setting to another, it is advisable to first place the run/hold/off
operational theory of each card on an individual basis.
switch in hold. This position keeps the counter from running past the time at which it was first inhibited by introducing a
manual inhibit signal. After the new setting has been made, returning the switch to the run position will then allow the counter
b. Definitions Applicable to DMS Digital Circuits.
to advance to the new time. The counter inhibit circuit is disabled by the off position of the switch, thus allowing normal time
sequencing of all circuits.
(1) Digital circuit. A circuit whose output is always at one of two permissible discrete voltage levels (HIGH or LOW) in
response to the input(s) from other digital circuits. If there is more than one output, some may be at LOW level, and some
(2) Peak detector. The peak detector section is designed for reading the peak amplitude of low frequency signals
may be at HIGH level. None will be in the intermediate prohibited level, except for the time of transition from one level to
used in checking the response of circuits in the MTS and tracker electronics. An adjustment is also provided for calibrating the
another.
amplitude of the reference oscillator contained in the trainer section.
(2) Low voltage level. Also called "LOW" or "ZERO" is a voltage between 0.0 Vdc and +0.4 Vdc.
(a) Read switch S28 is spring-loaded and must be actuated (and held) in order to observe the output of the peak
detector through position E20 of the selector switches. In the "normal" position, the sample/hold capacitor of the peak detector
(3) High voltage level. Also called "HIGH" or "ONE" is a voltage between +2.40 Vdc and +5.50 Vdc.
is discharged, thus preparing it for a new signal input.
(4) Integrated circuit (IC). A monolithic, and therefore nonrepairable circuit consisting of (usually many) transistors,
(b) In testing the MTS, discrete frequencies of 0.5, 1.0, 5.0 and 10.0 Hz are applied to the horizontal and vertical
diodes, and resistors on a single silicon chip.
rate/position inputs. The response of the derate and filter networks is then measured by observing the attenuated output of
each channel. Similarly, the tracker electronics is tested with frequencies of 0.5 and 5.0 Hz, and the rate/position outputs (after
c. Logic Families used in DMS. The two families of logic circuits are: Diode Transistor Logic and Transistor-Transistor
derating in the DMS-D) are monitored for the correct signal levels. In order to read the output of the horizontal filter (MTS) or
Logic. Note the input diodes and output transistor in figure 3-9 A. This type of circuit is called Diode-Transistor Logic (DTL).
horizontal derate (tracker electronics) circuits, horiz/ref/ vert switch S27 must be set to the horiz position. Depending on which
Note the input transistor and output transistors in figure 3-9 B. This type of circuit is called Transistor-Transistor Logic (TTL).
of the UUT's is connected, the peak detector will then read the peak level of the incoming horizontal signal. Setting the
The input diodes in the DTL circuits perform a logic function ("AND"). The diodes at the inputs of the TTL gates do not perform
horiz/ref/vert switch to vert will select the vertical channel in a like manner. In the ref position of the switch, the UUT stimuli is
a logic function, but clamp the negative undershoots at
selected, which has a nominal amplitude of 3.000 VP, independent of frequency. This reference amplitude may be adjusted, if
required, by means of lo freq amptd
3-17
