TM 9-4935-481-14-1
C4
1. The divide by 10 TC output of the first stage is HIGH.
4.5 Vdc across the second forward biased zener is verified at TP3. This voltage input is buffered by AR5 and fed to voltage
comparator AR4. The circuit consisting of AR3, AR4 and AR5 is tested by applying a +5 Vdc level to the P1-6 input and then
2. The divide by 10 TC output of the preceding stage is HIGH.
varying the P1-7 voltage input from +4.950 Vdc to a higher voltage level until the P1-2 output produces a positive going
spike approximately .5 psec at >2.5 Vdc. The width of the output pulse is determined by resistor R11 and capacitor C13.
(c) This creates an enable window one clock period wide for every HIGH of the divide by 10 TC output of the
The above test is repeated with a -5 Vdc being applied to P1-6, and a negative variable voltage applied to P1-7. The output
preceding stage. Therefore, the following stage advances by one count for every 10 counts of the preceding stage.
spike at P1-2 will be negative going. The circuit of AR6, AR7 and AR8 is tested in the same manner as described above.
(d) The outputs of the BCD counters are as follows:
2. Digital logic circuits . A description of the digital logic circuits will be found in Chapter 3, paragraph 3-3 (b
1. Z4 - pin 15 - a 1 psec wide clock pulse that goes LOW every 10 ec.
s
through h) of this manual. A major portion of the circuit is tested by applying a step input LOW (<0.4 Vdc) and/or a step input
HIGH (>2.5 Vdc) to the appropriate pins on the circuit card and measuring for a HIGH or a LOW (whichever is required) on
2.
Z5 - pin 15 - a 10 ec wide clock pulse that goes LOW every .1 msec.
s
the corresponding output pins. Z1, Z2 and Z3 are "ONE-OF-TEN" decoder logic elements and are tested as follows. Clock
3.
Z6 - pins 14, 13, 12, 11 - .1, .2, .4 and .8 msec timing pulses, respectively
pulses with periods of .1, .2, .4 and .8 msecs are applied to pins 15, 14, 1 and 2, respectively of the logic elements. In the
test mode configuration resistors and bias voltage are connected across the output pins of Z1, Z2 and Z3 in such a
- pin 15 - a .1 msec wide clock pulse that goes LOW every 1 msec.
configuration as to generate the stair step waveform described in Table 2-17, TM 9-4935-482-40.
4. Z8 - pins 14, 13, 12, 11 - 1, 2, 4, 8 msec timing pulses respectively - pin 15 - a 1 msec wide clock pulse
(10) Vertical pulse simulator A - A10 (fig. 4-49) The A1O circuit card is performance tested using DMS-D, DMS-G and
that goes LOW every 10 msec.
test adapter A9, connector J1.
5. Z10 - pins 14, 13, 12, 11 - 10, 20, 40, and 80 msec timing pulses, respectively
(a) This circuit card generates the timing sequence required for testing the vertical guidance wire circuits in the
- pin 15 - a 10 msec wide clock pulse that goes LOW every 100
tracker test set. A description of the digital logic circuits will be found in Chapter 3, paragraph 3-3 (b through h) of this
manual.
msec.
(b) The circuit card reference fig. 4-49 (schematic, sheet 1) operates and is tested in the following manner: The
6. Z12 - pins 14, 13, 12, 11 - 100, 200, 400 and 800 msec timing pulses, respectively.
circuit consists of an internal 1 meg Hz oscillator Y1, gating logic, BCD decade counters and "ONE-OF-TEN" decoders.
(e) The outputs (pins 14, 13, 12 and 11) of counters Z6, Z8, Z1O and Z12 are connected to "ONE-OF-TEN"
When card pin Pl-118 is HIGH the internal 1 meg Hz clock is applied syncronously to all six BCD decade counters. Count
decoders Z7, Z9, Z11 and Z13, respectively. The outputs of Z9, Z11 and Z13 are also connected to OR gates Z14 and Z15.
enable input pin 10 of the first counter (Z4) is connected to +5 Vdc and count enable input pin 7 is open, therefore, this
In the test mode configuration, resistors and bias voltage are connected to the outputs of Z7, Z9, Z11 and Z13 in such a
counter is continuously enabled and counts as long as the clock pulses are present. The second counter (Z5) is enabled only
configuration as to generate the stair step waveform described in the test procedure. The outputs of Z14 and Z15 are
during the terminal count (TC) of the divide by 10 of the first counter. The duration of the TC pulse is equal to the period of
monitored for the waveforms described in the test procedure.
the clock wave, therefore, for every 10 clock pulses counted by the first counter, the second counter counts only one pulse.
It takes 10 input pulses to the second counter to produce one pulse at its TC output, therefore, it takes 10 x 10 or 100 clock
(f) All counters can be reset by applying a LOW to either Pl-104 or P1-107. The internal 1 meg Hz clock may be
pulses to produce a pulse at the TC output of the second counter. The remaining stages (Z6, Z8, Z1O, Z12) are enabled only
inhibited by applying a LOW to Pl-118.
if both of the following conditions are met.
3-30.7
