TM 9-4935-481-14-1
C4
Capacitor C12 is required to prevent oscillations and improves the power supply noise rejection of the amplifier AR5. Q4 is
accuracy of the 13V input and the accuracy of the 1.74K resistor, since the summing junction (at pin 2) of the high gain
the current booster transistor.
operational amplifier AR1 is virtually at 0 Vdc. The output voltage of the preregulator is obtained on the emitter of the
booster transistor Q1.
(h) The scaling and buffering circuit for the -5 Vdc reference voltage is made of R22, R23, R24, R25, AR6, C13,
R26, R27 and Q5. This circuit operates in the same manner as the -2.5V circuit.
(c) The second stage consisting of R4, R5, AR2, C7, VR2 and R31 is the final regulator. VR2 is a temperature
compensated reference diode. The zener current for this diode is generated by applying the output voltage of the
(i) Master clock and counters (digital circuit). (Refer to Chapter 3, paragraph 3-3 (b through h) of this manual for
preregulator to the series combination of R4 and R5. The nominal value of this current is 7.5 ma. The output voltage of the
fundamentals of digital circuits). This circuit consists of the internal 10 KHz oscillator Y1, gating logic, BDC decade counters,
preregulator at the Q1 emitter, while little dependent on temperature, may have a value between -8.55 Vdc and -9.45 Vdc
and output buffering gates.
due to the 5% tolerance of the IN939B type diode (VR1), therefore, in order to generate 7.5 ma current using this voltage, the
input resistance (R4 + R5) of the final regulator was made adjustable by approximately +10% from the nominal value of
(j) When card pins 63, 69, 65 and 67 are high, the internal 10 KHz clock is applied synchronously to all six BCD
1.20K by means of the R4 200W trim potentiometer. Resistor R31 is a current booster or pull up resistor, for the AR2
decade counters. The count enable inputs (pins 7 and 10) of the first counter are tied to +5 Vdc, therefore, this counter is
amplifier. The total current flowing into VR2 and into the third stage is approximately 9.23 ma, but the AR2 amplifier output
continuously enabled and counts as long as the clock pulses are present. The second counter is enabled only during the
current is rated at 5 ma, therefore, a booster is required. The nominal value of the current supplied by R31 is 8.84 ma (=
terminal count (TC) of the divide by 10 output of the first counter. The duration of the TC pulse is equal to the period of the
13V-9V 453Q), therefore, the amplifier is required to supply the nominal current of only 0.39 ma (= 9.23-8.84). The output
clock wave, therefore, for every 10 clock pulses counted by the first counter the second counter counts only one pulse, but it
voltage of the final regulator is virtually independent of the +13V power supply voltage variations in the range of 10 to 16
takes 10 input pulses to the second counter to produce one pulse at its TC output, therefore, it takes 10 x 10 or 100 clock
Vdc, and also independent of ambient temperature variations in the range of -20 C to +75C.
pulses to produce a pulse at the TC output of the second counter. The remaining stages (four) are enabled only if both of the
following conditions are met:
(d) The third stage provides four scaling and buffering circuits which convert the output of the final regulator into
four reference voltages: +5 Vdc ref, +2.5 Vdc ref, -2.5 Vdc ref, and -5 Vdc ref.
1. The divide by 10 (TC) output of the first stage is HIGH
(e) The circuit providing +5 Vdc is made of R6, R7, R8, AR3, C8, R9, R1O, Q2 and C9. The scaling-down of the
2. The divide by 10 (TC) output of the preceding stage is HIGH
final regulator output to +5 Vdc is accomplished by the voltage divider comprised of resistors R6, R8, and trim potentiometer
(k) This creates an enable window one clock period wide for every HIGH of the divide by 10 (TC) output of the
R7 for precise voltage adjustment. The output of the potentiometer is buffered by the unity gain non-inverting amplifier AR3
preceding stage, therefore, the following stage advances by one count for every 10 counts of the preceding stage.
which used booster transistor Q2. Capacitors C8 and C9 are required to prevent oscillations in the circuit.
(l) The outputs of the first BCD counter Z4, provides 0.1, 0.2, 0.4 and 0.8 mS timing pulses; Z6 counter provides
(f) The scaling and buffering circuit for the +2.5 Vdc reference voltage is made of R11, R12, R13, AR4, C01,
1, 2, 4 and 8 mS timing pulses; Z10 counter provides 100, 200, 400 and 800 msec timing pulses; Z14 counter provides 10
R14, R15, Q3 and C11. This circuit operates in the same manner as the +5 Vdc circuit.
and 20 sec timing pulses.
(g) The scaling and buffering circuit for -2.5 Vdc reference voltage is made of R16, R17, R18, R19, AR5, C12,
(m) All timing outputs are buffered using two-input AND gates with the two inputs tied together.
R20, R21 and Q4. These components are connected in the inverting amplifier configuration. The input resistance is equal to
the series combination of resistor R17 and trim potentiometer R16 (gain adjustment). R18 is a feedback resistor. R19 is a
(n) All counters can be reset by applying a LOW to either pin 65 or pin 67
current offset compensating resistor. R20 protects transistor Q4 from excessive base current due to inadvertant overload.
3-30.10
