TM 9-4935-481-14-1
C2
(i) AR12 has a gain of -0.101 to -0.108, determined by resistors R38, R39 and potentiometer R40. R40 is
(b) The circuit card operates and is tested in the following manner. VR1 is a 15V regulator which provides +15
adjusted until the output at TP6 is set to +0.2625 Vdc (nominal). The output of AR12 is scaled by resistors R42, R43. With
Vdc regulated voltage to the bias input (pin +V) of operational amplifier AR4 and to output pin P1-7. Q1, connected to the
relay K10 and K11 energized the output at TP4 is -0.475 Vdc (nominal).
output of VR1, provides current boost capability. Potentiometer R3 is adjusted so the output of VR1 (pin 8) is set to +15 Vdc
(nominal).
(j) With K3 energized the voltage input at P1-44 is connected to the noninverting input of buffer AR5 and is
monitored at P1-42. With a gain of +1.05 the output of AR8 is -5.25 Vdc (nominal) and is monitored at P1-39 when K8 is
(c) A -5 Vdc reference voltage is connected to the non-inverting inputs of buffer AR1 and operational amplifier
deenergized. With a gain of -0.42 the output of AR9 is +1.05 Vdc (nominal).
AR8. The DC offset of the AR1 circuit is adjusted by potentiometer R5 to -5.0 Vdc (nominal) and is connected to scaling
resistors R6, R7 and R8 and relay K1. Relays K1 and K2 are energized as required to select the proper voltage to the non-
(k) A +2.5 Vdc reference voltage is connected to the inverting input of operational amplifier AR1O. With a gain
inverting input of buffer AR2. The output of AR2 is connected, through relay K3, to the FET switch S1A. When +5 Vdc is
of -0.42 the output of AR10 is -1.05 Vdc (nominal) and is monitored at P1-39 when K7 and K8 are energized.
applied to P1-63, SlA switches and allows the input of pin 1 to be fed out pin 2 to the non inverting input of AR3.
NOTE
(d) With +5 Vdc applied to P1-62, FET switch S1B is turned ON. With S1B ON, a ground is applied to the input
of AR3. Potentiometer R12, is adjusted to provide 0 Vdc (nominal) output voltage at P1-21.
The waveforms shown in fig.
4-52 (schematic) are system
waveforms which are applicable to the circuit performance when the
(e) A -2.5 Vdc reference voltage at P1-54 is connected to the inverting inputs of operational amplifiers AR6, AR8
assembly is installed in DMS-D, but which do not necessarily apply
and AR9. With a gain of -0.196 to -0.203, determined by resistors R16, R17 and potentiometer R18, the output of AR6 is set
to the circuit performance while tested in DMS-G.
to +0.5 Vdc (nominal) and is monitored at P1-21 when relay K6 is energized and K5 is deenergized. The output of AR6 is
connected to the inverting input of operational amplifier AR7. With a gain of -1, the output of AR7 is -0.5 Vdc (nominal) and
(14) Master clock and counter, and voltage reference - A14 (fig. 4-53) The A14 circuit card is performance tested
is monitored at P1-21 (TP4) when K5 and K6 are energized.
using DMS-D, DMS-G and test adapter A10, connector J1.
(f) With a gain of -0.101 to -0.108, determined by resistors R32, R33 and potentiometer R34, the output of AR11
(a) The circuit of this assembly consists of analog and digital integrated circuits, transistors, and passive
is adjusted to -0.2625 Vdc (nominal) and is scaled by resistors R36 and R37.
components. The digital portion of this circuit is tested by applying digital low and/or high stimulus to appropriate pins on
connector P1 of the assembly and verifying appropriate outputs (on the same connector). The analog portion of this circuit
(g) The output of AR3 is connected to the inverting input of operational amplifier AR4. The output of AR4 is
does not require external signals except +13 Vdc power. Operation of the analog and digital circuitry is explained below in
connected to transistors Q2 and Q3 which are a complementary pair and connected in a configuration to provide current
that order.
drive capability. The AR4, Q2 and Q3 configuration provides a closed loop gain of -2.00 to -2.02 determined by resistors R9,
R11 and potentiometer R10O. With relay K2 energized and K3, K4 and K6 deenergized, the output of AR4 is adjusted (by
(b) The voltage reference circuit (analog) has three stages. The first stage consisting of R1, AR1, C4, VR1, R2,
potentiometer R10) to +7.686 Vdc (nominal) at TP4 with no load at P1-21.
Q1 and R3 is a preregulator. VR1 is a temperature compensated reference diode. The zener current for this diode is
generated by applying +13 Vdc to R1. The nominal value for this current is 7.5 mA and does not depend on the voltage at
(h) The output of AR11 is connected, through relays K9 and K11, to the noninverting input of buffer AR13. With
which VR1 regulates. It depends only on the
+5 Vdc applied to P1-61, the output of AR13 is connected, through FET switch S2, to the non-inverting input of buffer AR3.
Potentiometer R44 is adjusted until the output at TP4 is set to +0.5250 Vdc (nominal). With relay K9 energized the output at
TP4 is +0.475 Vdc (nominal).
3-30.9
