TM 9-4935-481-14-1
C2
on the card connector.
(f) The output of the voltage divider is connected through R35 to the unity gain non-inverting buffer AR5.
Resistor R35 protects AR5 from overload in case of inadvertant short from pin 51 on connector P1 to ground. Resistor R35
(o) The internal 10 KHz clock may be inhibited by applying a LOW to pin 69 on the card. When a LOW is
together with capacitor C14 serves as a noise filter at the input to AR5. Trim potentiometer R36 provides an offset
applied to pin 63 on the card the external (TTS) clock is applied to the counters in place of the internal clock.
adjustment (cancellation) for AR5 buffer.
(p) AR7 serves as a line receiver and pulse shape restorer for the external (TTS) clock. AR7 is a voltage
(g) The output of AR5 buffer is connected to the inverting amplifier consisting of operational amplifier AR6 and
comparator, with the threshold voltage of approximately 1.0 Vdc set by voltage divider R28 and R32.
associated passive components. The gain is determined by the ratio R38 R37. Resistor R39 minimizes the voltage offset
at the output of AR6.
(15) Trainer performance A - A15 (fig. 4-54)
(h) Operational amplifier AR7 with associated passive components form a non-inverting amplifier with a gain of
This assembly is performance tested using DMS-D, DMS-G, and test adapter All, connector J1.
1.5 (nominal) determined by the ratio (R41 + R42 + R43) R41. Trim potentiometer R43 provides a gain adjustment of
(a) This circuit consists of digital integrated circuits whose operation is described in Chapter 3, paragraph 3-3 (b
approximately 6.7%. The input to this amplifier is +5.000 Vdc which produces 7.5 Vdc at the output. This output is
through h) of this manual.
connected to three voltage dividers. The voltage divider consisting of R44, R45, and R46 produces +1.980 Vdc and +0.941
Vdc. The voltage divider consisting of R47, R48, and R49 provides 0.992 Vdc, and 0.406 Vdc. The voltage divider consisting
(b) The circuit is tested by applying digital LOW and/or HIGH stimulus to appropriate pins on the connector P1
of R55, R56, R57 and R58 provides +4.000 Vdc, +0.992 Vdc and +0.411 Vdc.
and verifying corresponding outputs under simulated load conditions.
(i) AR8 serves as a unity gain non-inverting buffer for the first two of the dividers described above. R50 protects
(16) Trainer performance B - A16 (fig. 4-55)
AR8 in case of an output short-circuit. C23 together with R50 provide noise filtering at the input to AR8. Trim potentiometer
This assembly is performance tested using DMS-D, DMS-G, and test adapter A12, connector J1.
R51 provides an offset voltage adjustment (cancellation) at the output of AR8. The output of AR8 is connected to the
inverting amplifier consisting of operational amplifier AR9 and associated passive components. The gain magnitude of this
(a) The circuits consist of operational amplifiers, relays, and passive components.
amplifier is determined by the ratio R53 + R52. Resistor R54 minimizes the offset voltage at the output of AR9.
(b) AR1 is a unity gain non-inverting buffer. Resistors RI and R2 protect the buffer from overload in case of
(j) AR12 serves as a unity gain non-inverting buffer for the voltage divider consisting of R55, R56, R57 and R58.
inadvertant short from pin 57 to ground.
Resistor R64 protects AR12 in case of an inadvertant short from pin 29 on connector P1 to ground. Capacitor C35 together
(c) Operational amplifier AR2 and associated components form an inverting amplifier whose nominal gain is
with resistor R64 provide noise filtering at the input to AR12. Trim potentiometer R65 provides an offset voltage adjustment
0.0357. The gain is determined by the ratio (R4 + R5) . R3. Trim potentiometer R5 provides a 25% gain adjustment.
(cancellation) at the output of AR12.
(d) Relays K1 through K14 have control input at pin 9. The 2K ohm resistor at this input limits the control current.
(k) AR10 and associated passive components function in the same way as AR12 and its associated components.
Having two buffers (AR1O and AR12) for the last voltage divider permits using two different outputs of this divider at the
(e) AR3 is a unity gain non-inverting buffer. R22 is the offset adjustment. Resistors R21 and R23 protect the
same time.
buffer from overload in case of inadvertant short from pin 60 on connector P1 to ground. The output of the AR3 buffer
(nominal 2.500 Vdc) is connected to the voltage divider consisting of resistors R28 through R34. Voltages (nominal) of
(l) The output of AR10 buffer is connected to the inverting amplifier consisting of AR11 operational amplifier and
+2.500 Vdc, 540 mVdc, 265 mVdc, 181.25 mVdc, 128.5 mVdc, 99.5 mVdc, and 82 mVdc can be obtained at the output of
associated components. The gain magnitude of this amplifier is determined by the resistance ratio R62 . R61. Resistor
the voltage divider (pin 23 on connector P1) by energizing relays K1 through K7, respectively.
3-30.11
