TM9-4935-481-14-1
C2
(8) Rate position simulator B - A8 (fig. 4-47)
(h) A -5 Vdc reference voltage is connected to the non-inverting input of buffer AR15. The output of AR15 is connected,
The A8 circuit card is performance tested using DMS-D, DMS-G and test adapter A11, connector J4.
through FET switch S5A, to the non-inverting input of buffer AR16. The output of AR16 is monitored at P1-59 when relay K6
is energized. FET switch S5B, when turned ON, provides a ground input to AR16.
(a) This circuit card is used to scale the rate position voltage required for performance testing the tracker test
set. (b) The circuit card operates and is tested in the following manner. A -5.0 Vdc reference voltage is connected to the
NOTE
non-inverting input of operational amplifier AR1. With an adjustable gain of +1.476 to +1.536 the output is adjusted, by
potentiometer R3, to -7.500 Vdc (nominal).
The waveforms shown in fig. 4-47 are system waveforms which are applicable to the
circuit performance when the assembly is installed in DMS-D, but which do not
(c) The output of AR1 is connected to a bank of scaling resistors R5 through R12 and to the inverting input of
necessarily apply to the circuit performance while tested in DMS-G.
operational amplifier AR2. With a gain of -0.60 the output of AR2 is +4.50 Vdc (nominal) and is connected to K9-3 and the
non-inverting input of operational amplifier AR3. With a gain of +1.3555 the output of AR3 is +6.100 Vdc (nominal) and is
(9) Clock Inhibit and counter conditioning - A9 (fig. 4-48)
connected to K9-6. With K7 and K9 energized, the outputs of AR2 and AR3 are monitored at P1-59 and P1-60, respectively.
By proper selection of relays K1 through K4 the voltages across the scaling resistors are connected to AR4 and AR5 via FET
The A9 circuit card is performance tested using DMS-D, DMS-G and test adapter A9, connector J3.
switching circuits S1A and S2A. FET switches S1B and S2B, when turned ON, provide a ground input to buffers AR4 and
AR5, respectively. The outputs of AR4 and AR5 are connected to the inverting input of AR9 and AR11, respectively.
(a) This circuit card generates the clock inhibit required for testing the tracker test set. It also includes counter
conditioning circuits and generates some required reference voltages.
(d) A +2.5 Vdc reference voltage applied to P1-4 is connected, through a resistive voltage divider, consisting of
R19 and R20, to FET switch S3A which is in turn connected to the non-inverting input of buffer AR6. The voltage divider
(b) The circuit card operates and is tested in the following manner:
attenuates the input voltage to 0.5 Vdc (nominal). FET switch S3B, when turned ON, provides a ground input to AR6. The
output of AR6 is connected to the inverting inputs of AR9 and AR11. AR9 through AR12 each have a gain of -1.0. The
1. Analog logic circuits. A +5.0 Vdc reference voltage is connected to the non-inverting input of operational
outputs can be measured at P1-59 and P1-60 by proper selection of relays K5 through K8.
amplifier AR1. With a gain of +1.9 the output of AR1 is +9.50 Vdc (nominal) and is connected to P1-24 and the inverting
input of operational amplifier AR2. With a gain of -1 the output of AR2 is -9.50 Vdc and is monitored at P1-22. A +5.0 Vdc
(e) A -5.0 Vdc reference voltage is connected to the non-inverting input of operational amplifier AR7. With a
reference voltage is connected to the non-inverting input of operational amplifier AR9. With a gain of +1.08 the output of
gain of +1.8 the output of AR7 is -9.0 Vdc (nominal) and is monitored at P1-13.
AR9 is +5.400 Vdc (nominal) and is monitored at P1-36. In the test mode configuration a 20K ohm potentiometer is
connected from P1-22 (-9.5 Vdc) to P1-24 (+9.5 Vdc). The output of this potentiometer is connected to the non-inverting
(f) A +5.0 Vdc reference voltage is connected to the non-inverting input of operational amplifier AR8. With a
input of buffers AR3 and AR6, which is P1-6 and P1-11, respectively. To verify the dc offset of AR3, a zero voltage is
gain of +1.8 the output of AR8 is +9.0 Vdc (nominal) and is monitored at P1-14.
applied to P1-6 (AR3 pin 3) and a zero voltage is verified, within 6 MV, at P1-3 output. VR1 and VR2, which are +12 V
zener's, are tested by applying first a plus 24 Vdc level and then a -24 Vdc level into P1-7, through R20, across the back to
(g) A +5 Vdc reference voltage is connected to the non-inverting input of buffer AR13. The output of AR13 is connected,
back zener combination. The zenered voltage plus a voltage drop of
through FET switch S4A, to the non-inverting input of buffer AR14. The output of AR14 is monitored at P1-60 when relay K6
is energized. FET switch S4B, when turned ON, provides a ground input to AR14.
3-30.6