TM 9-4935-481-14-1
C2
(c) The purpose of the zener diode VR1 is to limit the HIGH to approximately +3.0 Vdc and the LOW to
NOTE
approximately O Vdc. If the zener diode VR1 was removed or opened, the output of the comparator would go to
approximately +12.5 Vdc in the High state, and to approximately -12.5 Vdc in low state.
The waveforms shown in fig. 4-56 (schematic) are system
waveforms which are applicable to the circuit performance when the
(d) Operational amplifiers AR2, AR3, AR4 and their associated components form three additional voltage
assembly is installed in DMS-D, but which do not necessarily apply
comparators which operate in the identical manner as
to the circuit performance while tested in DMS-G.
the comparator described above.
Table 3-1.2. Circuit Card A17 Lamp Driver
(e) Resistors R18 and R19 limit the control current to relays K2 and K3, respectively. The control voltage
required at P1-117 and P1-118 to energize the relays is 1.2 to 5.5 Vdc.
Pin Numbers Versus Functions
Pin
Function
NOTE
1
+24 Vdc power input
The waveforms shown in fig. 4-57 (schematic) are system
2
Control signal input
waveforms which are applicable to the circuit performance when the
3
Control signal input
assembly is installed in DMS-D, but which do not necessarily apply
6
Power and input signal return (ground)
to the circuit performance while tested in DMS-G.
8,9
Output voltage slew rate control (capacitor)
10
Output
(19) Tracker detector simulator A - A19 (fig. 4-58)
(18) Trainer performance D - A18 (fig. 4-57)
This assembly is performance tested using DMS-D, DMS-G, and test adapter A10, connector J2.
This assembly is performance tested using DMS-D, DMS-G, and test adapter A9, connector J4.
(a) The circuit of this assembly consists of analog and digital integrated circuits, transistors, and passive
components. The operation of this circuit is explained below.
(a) The portion of the circuit shown in fig. 4-57 (sheets 1 and 2) consists of digital integrated circuits whose
operation is explained in Chapter 3, paragraph 3-3 (b through h), of this manual. This circuit is tested by applying digital low
(b) The function of this assembly is to generate the following signals:
and/or high stimulus to appropriate pins on the connector P1 of the assembly, and verifying appropriate outputs (on the same
connector). The remaining portion of the circuit (shown in fig. 4-57, sheet 3) consists of operational amplifiers, relays, zener
diodes, and resistors. The operation of this circuit is explained below:
1. 1 KHz 286 mVP-P square wave
(b) The operational amplifier AR1, zener diode VR1, and resistors R14 and R15 form a voltage comparator. The
2. 20 Hz digital square wave
reference voltage (Vref) for this comparator is +5 Vdc which is applied to P1-8. This reference voltage, together with
3. 4.327 [cos (2p20t)]
resistors R14 and R15, determines the limit voltage of this comparator as shown by the equation Vlimit = -Vref (R15 R14).
When the values are substituted in the right side of this equation it yields Vlimit = -1.2475 Vdc. Therefore, the output of the
4. 4.327 [sin (2p20t)]
comparator will change state when the input voltage (at Pl-1O) passes through -1.2475 Vdc. When the input voltage is more
5. 1.750 [cos (2p20t)]
negative (e.g. -1.290 Vdc) than Vlimit, the output voltage will be approximately +3.0 Vdc which is called HIGH. When the
input voltage is less negative (e.g. -1.200 Vdc) than Vlimit the output voltage will be approximately O Vdc which is called
6. 1.750 [sin (2p20t)]
LOW.
3-30.14
