TM9-4935-481-14-1
C2
LOW (whichever is required) on the corresponding output pins. Z15 and Z16 are monostable flip flops which are triggered by
an input that switches from HIGH to LOW. The output Z15 is a 5.4 msec (nominal) pulse that switches from zero to +5 Vdc.
The pulsewidth is determined by resistor R24 and capacitor C17. The output of Z16 is a 1.5 msec pulse that switches from
Table 3-1. Circuit Card A7 Logic Levels
zero to +5 Vdc. The outputs from pins 6 and 8 are 180 degrees out of phase. AR6 is a lamp driver. In the test mode
configuration a 620 ohm resistor is connected for P1-57 to ground. The output (P1-57) is +23 Vdc (nominal) when the inputs
ELEMENT
PIN
STATE
to pins 2 and 3 of the lamp driver are HIGH. Capacitor C19 slows down the initial lamp driving current because when a lamp
is cold it would tend to draw a large amount of current.
Z17
3
0
NOTE
Z17
6
0
Z19
11
1
The waveforms shown in fig. 4-45 are system waveforms which are applicable to the
Z20
4,9(Q)
1
circuit performance when the assembly is installed in DMS-D, but which do not
Z20
5(reset)
0
necessarily apply to the circuit performance while tested in DMS-G.
Z20
6(Q)
0
Z21
3(Q)
0
(7) Rate Position Simulator A - A7 (fig. 4-46)
Z21
6(Q)
1
The A7 circuit card is performance tested using DMS-D, DMS-G and test adapter A11, connector J3.
Z21
8(Q)
1
Z21
11(Q)
0
(a) This circuit card generates the rate position timing logic required for testing the tracker test set. A description
Z22
8(Q)
0
of the digital logic circuits will be found in Chapter 3, paragraph 3-3 (b through h) of this manual.
(b) A major portion of the circuit card is tested by applying a step input LOW (<0.4 Vdc) and/or a step input
(d) The input to Z21 (pin 1) is +2.5 Vdc (nominal) and is generated by the +5.0 Vdc bias voltage and the divider
HIGH (>2.5 Vdc) to the appropriate pins on the circuit card and measuring for a HIGH or LOW (whichever is required) on the
circuit consisting of R2 and R3.
corresponding output pins. The circuit consisting of digital logic elements Z17, Z19 through Z22 and associated passive
components is used to generate 50 msec and 146 msec single shot pulses.
(e) The input to P1-120 is switched to ground which enables the circuit and triggers a pulse generator which is
connected to P1-118. The time of pulse generator trigger and circuit enable is referred to as Ts. The pulse generator output
(c) The circuit operates and is tested in the following manner. Initially the circuit is reset by applying a
is two, 200 msec pulses with a period of 50 msec and the time from Ts to the first pulse is 10 msec. The pulse generator
momentary ground to Pl-ll9. Pl-110O, 118 and 120 are held at +5.0 Vdc (nominal). The momentary ground resets the circuit
output has the waveshape shown in fig. 3-30, P1-118.
elements to the logic level states shown in table 3-1 where "1" state is >2.5 Vdc and a "O" state is <0.4 Vdc.
(f) The divide by 2 flip flop (Z20) is connected to trigger only on the negative slope of the input pulse. However,
the flip flop cannot trigger until the reset line (pin 5) switches from the "0" state to the "1" state. This is accomplished in the
following manner. When P1-120 is switched to ground (Ts), R-S flip flop Z21 pin 8 switches from the "1" state to the "0"
state. This transition triggers monostable flip flop Z22 which triggers only on the negative slope of the input pulse. The
output of Z22 is a +5V peak, 146 msec (nominal) pulse.
(g) When the output of Z22 switches to the "1" state, the output of Z17 (pin 3) switches to the "1" state, enabling
the divide by two flip flop Z20. Z20 will now be triggered by the negative slope of the first input pulse from the pulse
3-30.4
