TM 9-4935-481-14-1
C2
(f) Resistors R12, R13 and R14 are tested by connecting them as voltage dividers and verifying the output
meg ohms @ 25 ) thus, preventing fast discharge of the hold capacitor C38. When relay K6 is deenergized, capacitor C38
C
voltage. Resistors R21, R22 and R23 are tested in the same manner.
discharges through resistor R47, and the voltage on the capacitor starts following the positive excursions of the input volt-
age.
(g) Resistors R10, R11, R19 and R20 are measured directly using the ohmmeter function of the DMM.
(k) The vertical derate network consists of R51, R52 and C42. The input to this network is at pin 6 of the card
(h) AR2 and AR4 are unity-gain non-inverting buffers. AR3 and associated components form a unity gain
and the output is at pin 7. The output can also be connected to the input of the peak detector by energizing relays K4 and
inverting amplifier. AR5 and associated components form an inverting unity gain summing amplifier. All these amplifiers
K5.
and buffers are tested by applying known inputs and verifying appropriate outputs. Relays K1 through K4 control the routing
of the input signals and phase relationship of the output signals. These relays are tested by verifying appropriate outputs for
(l) The horizontal derate network consists of R53, R54 and C43. The input to this network is at pin 3 of the card
a given combination of the energized relays.
and the output is at pin 2. The output can also be connected to the input of the peak detector by energizing relays K3, K4
and K5.
(22) Tracker detector simulator D - A22 (fig. 4-61)
NOTE
This assembly is performance tested using DMS-D, DMS-G, and test adapter All, connector J2.
The waveforms shown in fig. 4-61 (schematic) are system waveforms which
are applicable to the circuit performance when the assembly is installed in
(a) The circuit of this assembly consists of analog integrated circuits, two modular analog multipliers, relays, and
DMS-D, but which do not necessarily apply to the circuit performance while
passive discrete components. The operation of the circuit is described below.
tested in DMS-G.
(b) The output voltage of the inverting summing amplifier consisting of AR1 and associated components is given
by the formula:
(23) Trigger simulator A23 (fig. 4-62)
Vout = -R3 {(V5 R4) + [V58 (R1+R2)]}
where: V5 = Voltage at P1-5 (zero or -5 Vdc)
This assembly is performance tested using DMS-D, DMS-G, and test adapter All, connector J3.
V58 = Voltage at P1-58 (+5.000 Vdc nominal)
(a) The circuit of this assembly consists of digital and analog integrated circuits, relays, and passive components.
The operation of the digital circuits is explained in Chapter 3, paragraph 3-3 (b through h) of this manual. The operation of
(c) The purpose of trim potentiometer R1 is to provide adjustment compensation for the dc offset contributed by
the analog circuits is explained below.
operational amplifier AR1.
(b) Operational amplifier AR1 and associated components form a differential input amplifier which has gain of 8.
PP
(d) The output of AR1 is connected to one input (pin C) of the analog multiplier Z1. A 5 KHz, 5.0 V sinusoidal
wave with a +2.476 Vdc component, is applied to the second input (pin D) of the multiplier Z1. The output voltage (at pin K)
(c) AR3 is a voltage comparator with a threshold voltage of -1 Vdc set by the voltage divider consisting of R9 and
of this multiplier is equal to 1/10 of the product of the two inputs. By applying known inputs and measuring the output, the
R10.
accuracy of the multiplier is verified and adjusted when necessary. R7 is the first-input zero adjustment potentiometer. R8 is
(d) AR4, AR5, AR6, AR8, AR10 and AR12 are unity gain non-inverting buffers.
the second-input zero adjustment potentiometer, and R9 is the output zero adjustment potentiometer. R6 is the scale factor
adjustment potentiometer providing approximately 10% adjustment of the nominal 1/10 scale factor.
(e) AR7 and AR11 are operational amplifiers connected as unity gain non-inverting buffers.
(e) Multiplier Z2 accepts two external outputs, one from P1-5 and the other from P1-56. The operation and checkout of this
(f) Operational amplifier AR9 and associated components form an inverting amplifier with a gain of 5.
multiplier is the same as for Z1.
3-30.19
