TM 9-4935-481-14-1
C2
or R32, and C20. This RC network provides a 1.1 msec delay-when relay K1 is deenergized or a 2.2 msec delay when relay
(c) The 1 KHz square wave is generated as follows: A 10 KHz digital square wave is applied to P1-114 and then
K1 is energized. The 1.75 cos (2p20t) signal is brought out on pin 6 of the card through unity gain non-inverting buffer AR6.
to the input of the decade counter Z1. The output of Z1, which is a 1 KHz digital square wave, is applied to the switch driver
consisting of R37, R38, R39, Q3, CR2 and C24. The output of the switch driver is applied to the gate of the analog switch
(i) The 1.75 sin (2p20t) signal is obtained by attenuating the 4.327 sin (2-20t) wave using the voltage divider
(junction FET) Q4. When the output of Z1 is LOW, transistor Q3 is ON and its collector is at approximately +4.8V. Diode
consisting of R18, R19, R22 and R24. The output of this voltage divider is applied to the RC network composed of R20, R21,
CR2 is back biased causing Q4 to conduct. When the output of Z1 is HIGH, transistor Q3 is OFF and its collector is at
or R23 and C17. This RC network provides a 1.1 msec delay when relay K1 is deenergized or a 2.2 msec delay when relay
approximately -13V. Diode CR2 is forward biased and the gate of Q4 is at -13V, thus turning Q4 off. The input of the switch
K1 is energized. The 1.75 sin (2p20t) signal is brought out to pin 4 of the card through unity gain, non-inverting buffer, AR5.
is applied to a scaling and reference shifting amplifier consisting of R41, R42, R43, R44, R45, C29, C30 and AR8. R41 is an
input resistor and R44 is a feedback resistor. The ratio of R44 to R41 is the scaling factor. The series combination of R42
(20) Tracker detector simulator B - A20 (fig. 4-59)
and R43 provides a -2.5V offset bias to the +2.5P (5VPP) input square wave of AR8. This results in the AR8 output square
This assembly is performance tested using DMS-D, DMS-G, and test adapter A10, connector J2.
wave switching between zero and 286 mV.
(a) The circuit of this assembly consists of analog and digital integrated circuits, transistors, relays, and passive
(d) Capacitors C29 and C30 are required to prevent oscillations. The signal is brought out on pin 50 of the card.
components. Refer to Chapter 3, paragraph 3-3 (b through h), of this manual for fundamentals of digital circuits operation.
(e) The 20 Hz output of P1-112 is divided down from the 1 KHz output of Z1. The output of Z3 is a 20 Hz
The operation of the circuit when performance tested using DMS-G is explained below:
symmetrical (equal low and high duration) square wave. The output is also fed to switch driver Q2, R34, R35, R36 CR1 and
(b) The dc/dc converter-regulator VR1 accepts +13 Vdc at pin 1 and generates +5 Vdc at pin 2. This output
C23. The operation is the same as described for the Q3 driver circuit.
voltage supplies digital integrated circuits Z1 through Z3, switching transistors, Q1, Q6, Q7 and Q8, and voltage comparators,
(f) The 4.327 cos (2p20t) wave is generated by taking the 20 Hz square wave output of analog switch Q1 and
AR2, AR4, AR6 and AR7.
applying it to the scaling amplifier composed of R1, R2, R3, R4, AR2 and C8 and then filtering the square wave with the
(c) Voltage comparators AR2 and AR4 act as zero crossing detectors when P1-17 and P1-19 are grounded.
narrow band-pass filter composed of R5, R6, R7, R8, R9, R1O, C9, C10, C13 and AR3. The filter is precisely tuned to the
When two sinusoidal quadrature (90out of phase) voltages are applied to these comparators, cosine (leading) to AR2 pin 1
input frequency using trim potentiometer R9. The amplitude of the cosine wave is adjusted using trim potentiometer R3.
and sine (lagging) to AR4 pin 1, the outputs of the comparators are two 50% duty-cycle square waves. If the sinusoidal
The 4.327 cos (2i20t) signal is brought out on pin 13 of the card.
voltages have (undersirable) dc offsets, or the voltage comparators have input offset voltages, the duty cycle of these square
(g) The 4.327 sin (2p20t) wave is generated by shifting (delaying) the 4.327 cos (2 20t) wave 90 degrees using
p
waves will differ from 50%. The purpose of trim potentiometers R5 and R1O is to compensate for these offsets. If the
the RC network composed of R11, C14, R12, R13 and C15 and then applying the output of this RC network to the non-
offsets are excessive, the trim potentiometers will not be able to compensate for them.
inverting amplifier consisting of AR4, R14, R15, R16, R17 and C16. The function of this amplifier is to provide buffering and
(d) The square wave output of AR4 will lag by 1/4 the period of the square wave output of AR2. With the input
gain to compensate for the attenuation of the RC network. The 4.327 sin (2 20t) signal is brought out on pin 11 of the card.
p
frequency of 20 Hz, 1/4 of the period is equivalent to 12.5 msec.
(h) The 1.75 cos (2p20t) wave is obtained by attenuating the 4.327 cos (2 20t) signal using voltage divider
p
(e) The outputs of AR2 and AR4 are compatible with DTL logic (see Chapter 3, paragraph 3-3 (b through h) of
consisting of R26, R27, R30 and R31. The output of this voltage divider is applied to an RC network composed of R28, R29
this manual). These outputs are connected to a
3-30.15
