TM9-4935-481-14-1
C2
consisting of AR4, C10, R38 and R39 is the peak detector. The output of the peak detector is connected to the non-inverting
input of buffer AR5.
(a) This circuit card generates the horizontal wire simulated voltage waveform, with ripple, required for
performance testing the Tracker Test Set (TTS). The voltage waveform is a 20 Hz square wave about an average dc level.
(h) Potentiometer R30 is adjusted to maximize the voltage at P1-2. This means that the monostable flip flop Z1
The dc average level is selected by use of FET switches S1A through S8A and S1B through S8B. The peak to peak level of
is set to trigger at the very peak of the sinewave.
the ripple signal is selected by the use of relays K3 and K4, which are connected across scaling resistors R44 through R48.
A calibrated dc voltage is provided at P1-14 for calibrating the TTS.
(i) In the test mode configuration, a 2K ohm potentiometer is connected from P1-8 to P1-10. The center tap of
the potentiometer is connected to +13 Vdc. With K19 and K20 energized, the potentiometer is adjusted to zero out any offset
(b) The circuit card operates and is tested in the following manner: A HIGH (open) or a LOW (<0.4 Vdc) input is
voltages in the circuits consisting of AR4, AR5 and AR6.
connected to P1-50. Pins P1-55 and P1-60 are open. The input signal is connected, through resistor R2 and diode CR1 to
transistor Q1. The output of Q1 is 180 degrees out of phase with the input signal and is connected, through R3 to transistor
NOTE
Q2. The output of Q2 switches to -13 Vdc when the input signal is LOW and to +5 Vdc when the input signal is HIGH. The
output of Q2 is connected, through a coupling circuit, to FET Q3. The coupling circuit, consisting of diode CR2 and capacitor
During performance and trouble shooting measurements, the waveforms shown in fig.
C7, insures that the input to Q3 does not exceed zero volts dc. The coupling circuit also allows Q3 to switch ON at a faster
4-42 will be applicable when a sinewave of 10.29 VPK is connected to P1-60.
rate.
(4) Horizontal wire simulator A - A4 (fig. 4-43)
(c) A +5 Vdc reference voltage is connected, through the non-inverting in- put of buffer AR1, to the drain
terminal of Q3. The output of AR1 is adjusted to +5.0 Vdc by potentiometer R1. The output of Q3 is +5 Vdc (nominal) when
The circuit card is performance tested using DMS-D, DMS-G and test adapter A10, connector J3.
the input to P1-50 is LOW and zero Vdc when the input to P1-50 is HIGH. This output is connected to the non-inverting input
of buffer AR2. The output of buffer AR2 is the same as its input.
(a) This circuit card consists of digital logic circuits and a filter capacitor C1. A description of the digital logic
(d) The output of AR2 and the -2.5 Vdc reference voltage applied to P1-54 is connected to the inverting input of
operational amplifier AR11. The two signals are summed by AR11. With a gain of -1 the output of AR11 is +2.5 Vdc or -2.5
(b) The circuit card is tested by applying a step input LOW (<0.4 Vdc) and/ or a step input HIGH (>2.5 Vdc) to
Vdc depending on whether the input to P1-50 is HIGH or LOW, respectively. The output of AR11 is connected to P1-46 and
the appropriate pins on the circuit card and measuring for a HIGH or LOW (whichever is required) on the corresponding
through relay K5, to scaling resistors R44 through R48.
output pins.
(e) The output of the scaling resistors is connected, through relays K3 and K4, to the non-inverting input of
buffer AR5. The output of AR5 is connected to the inverting input of operational amplifier AR6.
NOTE
(f) The -5.0 Vdc reference voltage applied to P1-31 is connected to the non-inverting input of operational
The waveforms shown in fig. 4-43 are system waveforms which are applicable to the
amplifier AR7. AR7 has an adjustable gain of +1.21 to +1.26. The output of AR7 is adjusted, by potentiometer R23, to -
circuit performance when the assembly is installed in DMS-D, but which do not
6.182
necessarily apply to the circuit performance while tested in DMS-G.
(5) Horizontal wire simulator B - A5 (fig. 4-44)
The A5 circuit card is performance tested using DMS-D, DMS-G and test adapter A11, connector J1.
3-30.2