TM9-4935-481-14-1
C2
NOTE
Vdc (nominal) and is connected to a bank of scaling resistors R28 through R39. The scaled voltage levels are selected by
applying the proper inputs to FET switches S1A through S7A.
The waveforms shown in fig. 4-44 are system waveforms which are applicable to the
circuit performance when the assembly is installed in DMS-d, but which do not
(g) The -2.5 Vdc reference voltage applied to P1-54 is connected to the inverting input of AR9 and non-inverting
necessarily apply to the circuit performance while tested in DMS-G.
input of AR8. In the test mode configuration a 5K ohm resistor is connected from P1-21 to P1-23 allowing AR8 to have a
gain of +2.97. The output of AR8 is -7.42 Vdc (nominal). With an adjustable gain of -.35 to -.36, (determined by resistors
(6) Horizontal wire simulator C - A6 (fig. 4-45)
R41, R49 and potentiometer R40) the output of AR9 is adjusted to +.8820 Vdc (nominal) and is connected to the non-
inverting input of AR10 and to a bank of scaling resistors R7 through R10. With a gain of +1.2 the output of AR10 is +1.058
The A6 circuit card is performance tested using DMS-D, DMS-G and test adapter A11, connector J2.
Vdc (nominal) and is measured at P1-21 when K1 is energized.
(a) This circuit card is used to scale the auto composite signal generated on circuit card A5 and to buffer and
(h) The voltages across the scaling resistors, R7 through R10, are selected by applying the proper input to FET
amplify some of the manual dc voltage levels. This card also generates some of the timing logic required for testing the
switches S7B, S8A, S8B and S9A. FET switch S9B is used to select a ground input for use during circuit card calibration.
tracker test set.
(i) The FET switches are turned ON by applying +5.0 Vdc to pin 4 or pin 6 of the switches. The outputs of the
(b) The circuit card operates and is tested in the following manner:
switches are connected, through non-inverting buffers AR3 and AR4, to the inverting input of operational amplifier AR6.
1. Analog logic circuits. A +2.5 Vdc reference voltage is applied to pin P1-52 and connected to the non-
(j) AR6 sums the two dc voltage input signals and generates th composite signal which can be varied by a
e
inverting input of operational amplifier AR1 which has an adjustable gain of +2.02 to +2.10. The output of AR1 is +5.150 Vdc
proper selection of the relays and FET switches.
(nominal) and is connected to a bank of scaling resistors R5 through R9. By proper selection of relays K2 through K7 the
scaled voltages are connected to the non-inverting input of buffer AR2 and are monitored at P1-29. +2.5 Vdc and -2.5 Vdc
(k) With P1-55 grounded, Q1, Q2 and Q3 are turned OFF. The output of AR2 is +5 Vdc (nominal). The input to
reference voltages are applied to P1-17 and P1-4, respectively. By proper selection of relays K1, K2, K5, K6 and K7 these
AR11 is +5 Vdc and -2.5 Vdc (from P1-54). With a gain of -1, the output of AR11 is -2.5 Vdc (nominal) and is measured at
voltages are connected to AR2 and are monitored at P1-29. A +5.0 Vdc reference voltage is applied to P1-32 and connected
P1-46.
to the non-inverting input of buffer AR3. The output of AR3 is connected to P1-34 and the inverting input of operational
amplifier AR4. A -5.0 Vdc reference voltage is applied to P1-15 and connected to the inverting input of operational amplifier
(l) With P1-60 grounded, Q2 and Q3 are turned ON. The output of AR2 is zero Vdc (nominal). The input to
AR5. In the test mode configuration a 10K ohm resistor is connected from P1-8 to Pl-10. With a gain of -0.176 the output of
AR11 is zero Vdc and -2.5 Vdc (from P1-54). With a gain of -1, the output of AR11 is +2.5 Vdc (nominal) and is measured at
AR5 is +0.880 Vdc (nominal) and is connected to the inverting input of AR4. AR4 sums the inputs from AR3 and AR5. With
P1-46.
a gain of -1 the output of AR4 will be -5.880 Vdc (nominal) and is connected, through relays K1 and K2 and buffer AR2, to
P1-29.
(m) A scaled voltage of -0.8820 Vdc (nominal) is connected to the non- inverting input of operational amplifier
AR12. With a gain of +1.2, the output of AR12 is -1.058 Vdc (nominal) and is measured at P1-23 when K1 is energized.
2. Digital logic circuits . A description of the digital logic circuits will be found in Chapter 3, paragraph 3-3 (b
Relays K1 and K2 are energized by applying a ground to P1-38.
through h) of this manual. The circuits are tested by applying a step input LOW ( 0.4 Vdc) and/or a step input HIGH (>2.5
<
Vdc) to the appropriate pins on the circuit card and measuring for a HIGH or
3-30.3