TM9-4935-481-14-1
C2
3-4.
DMS-D Electrical and Electronic Circuit Analysis
(b) The circuit card operates and is tested in the following manner: A 10 KHz clock pulse (+5 VP) is applied to
a. Circuit Card Operation. The following paragraphs describe the basic operation of circuit cards A1 through A24, 2A1
P1-114. Z1, which is a clocked flip flop, divides the clock pulse by 2. The output of Z1, pin 6, is a 5 KHz pulse (+5 VP) which
and 2A2 when tested using DMS-D and DMS-G. The text specifies amplifier gains, output voltages and waveforms as
is connected to a FET switch (S1). The +5.0 Vdc reference voltage, connected to P1-56, is applied through a non-inverting
related to the input test stimuli. Detailed circuit description is given only where the complexity of the circuit warrants such
buffer (AR3) to pin 1 of the FET switch. S1 is connected such that the output, pin 2, is HIGH (+5 VP) when the in- put clock
pulse is HIGH. S1 output impedance, pin 2 to pin 1, is 108 ohms minimum when the clock pulse is LOW. Since a virtual
consideration. In most cases, the description of the usage of individual components such as operational amplifier
compensation components and bias voltage filter components are not described in the text. For a detailed description of the
ground is maintained at AR2, pin 2, the voltage at S1, pin 2, will be approximately zero when the input clock pulse is LOW.
circuits, the operator is referred to the system theory of operation.
The output of S1, pin 2, then becomes a 5 KHz clock pulse with amplitude from zero to +5 Vdc. However, since S1 output
impedance is 108 minimum when the output signal is LOW, current cannot flow through resistors R7 and R8.
(1) Sum and diff signal simulator A - A1 (fig. 4-40)
(c) The -2.5 Vdc reference voltage, connected to P1-59 is applied through a non-inverting buffer (AR1) to
The A1 circuit card is performance tested using DMS-D, DMS-G and test adapter A10, connector J2.
resistor R5. Operational amplifier AR2 has a gain of -2.0 with respect to the -2.5 Vdc reference voltage and an adjustable
minus gain, provided by resistors R6, R8 and potentiometer R7, with respect to the 5 KHz clock pulse. The output of AR2 is
(a) This circuit card consists of digital logic circuits and passive components. The passive components are used
a 5 KHz clock pulse which traverses from -5 Vdc to +5 Vdc. Capacitor C9 is used for frequency compensation and to round
to differentiate digital output pulses and for controlling digital output pulsewidth. A description of the digital logic circuits and
off the leading and lagging edges of the clock pulse at the output of AR2.
the passive differentiating circuits used on this circuit card will be found in Chapter 3, paragraph 3-3 (b through h) of this
manual.
(d) The output of AR2 is connected to a 5 KHz roll off filter which shapes the 5 KHz clock pulse into a sinewave
symmetrical about zero Vdc. This filter net- work consists of resistors R15, R16, R17, R18 and capacitors C17, C18, C19
(b) The circuit card is tested by applying a step input LOW (<0.4 Vdc) and/ or a step input HIGH (>2.5 Vdc) to
and C20. The output of the roll off filter is connected to the non-inverting input of AR4 through a 60 Hz filter consisting of
the appropriate pins on the circuit card and measuring for a HIGH or LOW (whichever is required) on the corresponding
resistor R19 and capacitor C22. This filter is used to attenuate 60 Hz noise on the sinewave. The output of AR4 is a
output pins. The output pins are externally loaded with the proper loading resistors and bias voltages.
sinewave with an amplitude of 9.783 VP (nominal) and is adjustable by potentiometer R12.
NOTE
(e) AR4 output is connected to the non-inverting input of AR5 and to relay K1-3. K1 is energized only to monitor
and adjust the output of AR4. AR4 output is also connected, through a phase shift network consisting of resistor R24 and
The waveforms shown in fig. 4-40 are system waveforms which are applicable to the
capacitor C29, to the non-inverting input of AR6. The network will shift the phase of the input by approximately 90and will
circuit performance when the assembly is installed in DMS-D, but which do not
attenuate the input signal by a factor of .0106. With a gain of +21, the output of AR6 will be approximately 2.18 VP
necessarily apply to the circuit performance while tested in DMS-G.
(nominal).
(2) Sum and diff signal simulator B - A2 (fig. 4-41)
(f) The output of AR5, pin 6, is connected to transistors Q1 and Q2, which are a complementary pair connected
The A2 circuit card is performance tested using DMS-D, DMS-G and test adapter A10, connector J3.
in a configuration to boost the current drive capability. In the test configuration, a 2.49K ohm resistor is connected between
(a) This circuit card generates the sum and diff signals required for performance testing the tracker test set. A
buffer (AR10) and relay K4 are also provided for use during calibration of the collimator IR source control voltage.
3-30
